1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor memory.
2. Description of the Related Art
A semiconductor memory (DRAM: dynamic random access memory) is made up of a selection transistor and a capacitor. With the growing miniaturization of a memory cell due to improvement in microfabrication techniques, the decrease in the amount of charge storage of a capacitor has become problematic. FIG. 1 schematically illustrates a cross section of a structure of a DRAM in the process of manufacture using a conventional method. Lower electrodes 119 of the capacitor and bit lines 108 are already formed in The DRAM shown in FIG. Further, polysilicon plugs 116 serving as capacitive contacts for connecting selection transistors, not shown, to lower electrodes 119 are already formed as well.
The DRAM shown in FIG. 1 employs a COB (Capacitor Over Bit-line) structure in order to respond to the decrease in the amount of charge storage mentioned above. In particular, a cup-shaped (cylindrical) capacitor is formed over bit line 108 and the height of the capacitor is increased so that the surface area of lower electrode 119 is increased.
Polysilicon capacitive contact plug 116 has been formed by creating a contact hole opening between bit lines 108 using an SAC (Self Aligned Contact) etching technique which has a high etching selection ratio for silicon nitrides (bit line 108 and insulating film 109). However, the achievement of a finer design or a finer line for a memory cell causes difficulty in using the SAC etching. Also, a necessity has arisen to ensure a short margin between polysilicon plug 116 and bit line 108. In light of this, the diameter of each polysilicon plug 116 has recently been reduced, and polysilicon plug 116 has been formed using a non-SAC etching technique.
In order to form lower electrode 119, it is necessary to form a hole in silicon oxide film 117 by dry etching. However, the center of polysilicon plug 116 and that of lower electrode 119 are not in alignment with each other. In particular, in order to arrange lower electrodes 119 having high density, each of lower electrodes 119 is substantially elliptically formed with its major axis provided along the direction of a bit contact, not shown. Accordingly, a non-superimposed region is present between polysilicon plug 116 and lower electrode 119, and it is necessary that the hole mentioned above have a shape that conforms to the shape of lower electrode 119. Therefore, there is concern that, in forming the hole mentioned above by dry etching, a region corresponding to the non-superimposed region will be abnormally etched such that the hole will unavoidably reach bit line 108. An interlayer insulation film (silicon nitride film 111) has been formed for use as an etching stopper layer in dry etching. However, when removing silicon nitride film 111 at a later step, an interlayer insulation film (silicon oxide film 110) around polysilicon plug 116 is also etched, which results in forming a step in silicon oxide film 110. As a result, a step (unevenness) is also formed in the bottom face of lower electrode 119, as shown in FIG. 2. The step formed in the bottom face of lower electrode 119 is likely to induce an increase of leak current due to deterioration of coverage or concentration of an electric field in lower electrode 119. For this reason, after forming polysilicon plug 116, a pad (not shown) made of polysilicon having a larger diameter than plug 116 has been formed on plug 116. As a result, polysilicon plug 116 and lower electrode 119 are brought into conduction with each other through the pad. Details of conventional methods for manufacturing a semiconductor memory are described, for example, in Japanese Patent Laid-Open No. 2002-076302, Japanese Patent Laid-Open No. 2001-230383 and Japanese Patent Laid-Open No. 2000-277711.
The conventional methods for manufacturing a semiconductor memory have raised problems as follows:    (1) As already mentioned above, in order to form lower electrode 119 shown in FIG. 1, it is necessary to form a hole in silicon oxide film 117 shown in the figure by etching. However, when the aspect ratio (depth/diameter) of the hole is increased in order to increase the height of the capacitor, the diameter at the lower end of the hole becomes small relative to the diameter at the upper end of the hole. In addition, the diameter of polysilicon capacitive contact plug 116 tends to become smaller as mentioned above. As a result, the contact area between lower electrode 119 and polysilicon plug 116 is decreased and contact resistance is increased.    (2) Since polysilicon capacitive contact plug 116 is formed first, and then the polysilicon pad is formed on plug 116, the number of steps is increased.